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data sheet #: tm084 page 1 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets functional specification data sheet figure 1: functional block diagram description the STC4130 is a rohs compatible, integrated, single chip solution for the synchronous clock in sdh and sonet network elements. the device is fully compliant with itu-t g.812 type iii, g.813, and telcordia gr1244, and gr253. the STC4130 accepts 12 reference inputs and gen- erates 8 independent sy nchronized output clocks. reference input frequencies are automatically detected, and inputs are individually monitored for quality. active reference selection may be manual or automatic. all reference switches are hitless. syn- chronized outputs may be programmed for a wide variety of sonet and sdh frequencies. two independent clock generators provide the stan- dardized t0 and t4 functions. each clock generator includes a dpll (digital phase-locked loop), which may operate in the freerun, synchronized, and hold- over modes. both clock generators support master/ slave operation for redundant applications. connor- winfield?s proprietary synclink tm cross-couple data link provides master/slave phase information and state data to ensure seamless side switches. a standard spi serial bus interface or parallel bus provide access to the STC4130?s comprehensive, yet simple to use internal control and status registers. the device operates with an external ocxo or tcxo as its mclk at either 10 or 20 mhz. features ? for sdh sets and ssu ? for sonet stratum 3e, 3, 4e, 4 and smc ? complies with itu-t g.812 type iii , g.813, tel- cordia gr1244, and gr253 ? supports master/slave operation with the synclink tm cross-couple data link for master/ slave redundant applications ? accepts 12 individual clock reference inputs ? reference clock inputs are automatically fre- quency detected ? supports manual or automatic reference selec- tion ? t0 and t4 have independent reference lists and priority tables for automatic reference selection ? 8 synchronized output clocks ? output/input phase skew is adjustable in slave mode, in 0.1ns steps up to 200ns ? hit-less reference and master/slave switching ? phase rebuild on re-lock and reference switches ? better than 0.1 ppb holdover accuracy ? programmable bandwidth, from 90mhz to 107hz, for both t0 and t4 dpll ? supports spi or parallel bus interface ? ieee 1149.1 jtag boundary scan ? available in tq100 rohs package t0_master_slave t4_master_slave t0_xsync_in t4_xsync_in 12 ocxo tcxo 10mhz/ 20mhz serial/parallel bus interface control & status registers iee 1194.1 jtag phase digital to t4 digital phase activity & t0 active t4 active detector filter clock generator clock detector filter ref selector ref selector frequency offset monitor STC4130 reference clk lvds 155.52 mhz 8 khz 19.44/38.88/77.76 mhz 19.44/38.88/77.76 mhz 2 khz 1.544/3.088/6.176/12.352/24.704 mhz 2.048/4.096/8.192/16.384/32.768 mhz 44.736 mhz/34.368 mhz t0_xsync_out 1.544 mhz/2.048 mhz t4_xsync_out generator 8 khz 64 khz 1.544 mhz 2.048 mhz 19.44 mhz 38.88 mhz 77.76 mhz
data sheet #: tm084 page 2 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet table of contents description 1 features 1 STC4130 pin diagram (top view) 3 STC4130 pin description 4 absolute maximum ratings 6 operating conditions and elec trical characteristics 6 register map 7 general description 9 detailed description 10 chip master clock input 10 reference input monitoring and qualification 10 dpll active reference selection 11 manual reference selection mode 11 automatic reference selection mode 11 digital phase locked loop general description 11 free run 12 synchronized 12 holdover 12 dpll operating mode details 12 free run mode 12 holdover mode 13 output clocks 14 master/slave operation 15 processor interfac e descriptions 17 spi bus mode 17 serial bus timing 18 motorola bus 19 intel bus 21 multiplex bus mode 24 register descriptions and operation 26 general register operation 26 multibyte register reads 26 multibyte register writes 26 clearing bits in the interrupt status register 26 default register settings 26 application notes 40 mechanical dimensions 42 ordering information 42
data sheet #: tm084 page 3 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet STC4130 pin diagram (top view) note: pins labeled ?test pin? must be grounded. 26 76 51 ref5 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 30 29 34 32 36 31 28 35 33 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 77 78 79 80 81 82 83 84 85 86 87 90 91 92 93 94 95 96 97 98 88 89 99 100 ref7 ref8 ref9 t0_xsync_in t4_xsync_in bus_ad3 vdd18 bus_ad4 bus_ad5 bus_wrb vss bus_rdb bus_rdy bus_a0 bus_a1 bus_a2 bus_a3 bus_mode0 bus_mode1 clk7 avss clk0_n avdd18 vss tdo vdd33 avss reset bus_intr bus_ad0 bus_ad2 bus_ad6 bus_cs ref12 ref10 ref1 vdd33 ref3 t4_xsync_out bus_a4 bus_a5 bus_a6 vdd33 t0_xsync_out vss clk6 mclk_frq_sel te s t _ p i n vss trst clk0_p tck tms tdi vdd18 clk1 vss clk2 vdd33 clk3 vss clk4 vdd18 clk5 mclk ref2 ref4 ref11 vdd33 t0_ms ref6 t4_ms vdd33 bus_ad1 bus_ad7 bus_ale STC4130 vdd18 avdd18 vss te s t _ p i n vdd18 te s t _ p i n vss vdd18 vss vss vdd18 vss vss vdd33 vdd18 vdd18 vss vdd33 vss vdd18 vss vdd33 vss (tq100 package) see pg. 42 for mechanical dimensions
data sheet #: tm084 page 4 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet STC4130 pin description table 1: pin description pin name pin # i/o 1 description vdd33 6,22,31, 44,59, 69,80, 89,97 i 3.3v power input vdd18 9,18,27, 38,47,53, 65,73,84, 92 i 1.8v power input vss 3,13,15, 20,29,35, 41,49,56, 62,67,71, 78,82,87, 95 digital ground avdd18 1, 76 1.8v analog power input avss 75, 100 analog ground trst 94 i jtag reset tck 93 i jtag clock tms 91 i jtag mode selection tdi 90 i jtag data input tdo 88 o jtag data output reset 30 i active low to reset the chip mclk 99 i master clock input, 10 mhz or 20 mhz mclk_frq_sel 98 i master clock frequency select, 0 = 10 mhz or 1 = 20 mhz bus_mode0 63 i bus mode selection, 00: spi, 01: motorola, 10: intel, 11: multiplex bus_mode1 64 i bus mode selection, 00: spi, 01: motorola, 10: intel, 11: multiplex bus_cs 45 i parallel bus or spi chip select bus_ale 46 i parallel bus address la tch or spi clock input bus_wrb 48 i parallel bus write or spi data input bus_rdb 50 i parallel bus read or read/write input bus_rdy 51 o parallel bus ready output or spi data output bus_a6 61 i bus address bit 6 bus_a5 60 i bus address bit 5 bus_a4 58 i bus address bit 4 bus_a3 57 i bus address bit 3 bus_a2 55 i bus address bit 2 bus_a1 54 i bus address bit 1 bus_a0 52 i bus address bit 0 bus_ad7 43 i/o parallel bus address/data bit7
data sheet #: tm084 page 5 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet bus_ad6 42 i/o parallel bus address/data bit6 bus_ad5 40 i/o parallel bus address/data bit5 bus_ad4 39 i/o parallel bus address/data bit4 bus_ad3 37 i/o parallel bus address/data bit3 bus_ad2 36 i/o parallel bus address/data bit2 bus_ad1 34 i/o parallel bus address/data bit1 bus_ad0 33 i/o parallel bus address/data bit0 bus_intr 32 o interrupt ref1 2 i reference input 1 ref2 4 i reference input 2 ref3 5 i reference input 3 ref4 8 i reference input 4 ref5 10 i reference input 5 ref6 12 i reference input 6 ref7 14 i reference input 7 ref8 16 i reference input 8 ref9 17 i reference input 9 ref10 19 i reference input 10 ref11 21 i reference input 11 ref12 23 i reference input 12 t0_m/s 24 i select master or slave mode for t0, 1: master, 0: slave t4_m/s 28 i select master or slave mode for t4, 1: master, 0: slave t0_xsync_in 25 i cross-couple synclink tm data link input fot t0 for master/slave redundant applications t0_xsync_out 70 o cross-couple synclink tm data link output fot t0 for master/slave redundant applications t4_xsync_in 26 i cross-couple synclink tm data link input fot t4 for master/slave redundant applications t4_xsync_out 66 o cross-couple synclink tm data link output fot t4 for master/slave redundant applications clk0_p 85 o 155.52 mhz lvds output clk0_n 86 o 155.52 mhz lvds output clk1 83 o 19.44/38.88/77.76 mhz clk2 81 o 19.44/38.88/77.76 mhz clk3 79 o 8 khz frame pulse or 50% duty cycle clock clk4 77 o 2 khz frame pulse or 50% duty cycle clock clk5 74 o 44.736/34.368 mhz clk6 72 o 1.544/3.088/6.176/12.352/24.704/2.048/4.098/8.192/16.384/32.768 mhz clk7 68 o 1.544/2.048 mhz test_pin 7,11,96 i test pin, must be grounded for normal operation table 1: pin description pin name pin # i/o 1 description
data sheet #: tm084 page 6 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet absolute maximum ratings note 1: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. exposure to absolute maximu m rated conditions for extended periods may af fect device reliability. devices should not be operated outside the recommended operating conditions. operating conditions and electrical characteristics note 2: lvcmos 3.3 compatible note 3: for industrial temperature range (-40 to 85), use part number STC4130- i table 2: absolute maximum ratings symbol parameter min. max units notes vdd33 logic power supply voltage, 3.3v -0.5 4.5 volts 1 vdd18 logic power supply voltage, 1.8v -0.5 2.5 volts 1 v in logic input voltage, rel. to gnd -0.5 5.5 volts 1 tstg storage temperature -65 150 c 1 table 3: recommended operating condi tions and electrical characteristics symbol parameter min. nominal max. units notes vdd33 3.3v digital power supply voltage 3.0 3.3 3.6 volts vdd18 1.8v digital power supply voltage 1.65 1.8 1.95 volts v ih (3.3v) high level input voltage 2.0 5.5 volts 2 v il (3.3v) low level input voltage -0.3 0.8 volts 2 v oh (3.3v) high level output voltage (i oh = -12ma) vcc - 0.4 vcc volts 2 v ol (3.3v) low level output voltage (i ol =12ma) 0 0.4 volts 2 c in input capacitance 8 pf t rip input reference signal positive pulse width 10 ns t rin input reference signal negative pulse width 10 ns t a operating ambient temperature range 0 70 ? c 3 icc (vcc) 3.3v digital supply current 80 ma icc (vcc) 1.8v supply current 240 ma p d device power dissipation w
data sheet #: tm084 page 7 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet register map table 4: register map addr reg name bits type description 0x00 chip_id 15-0 r chip id, 0x4130 0x02 chip_rev 7-0 r chip revision number 0x01 0x03 chip_sub_rev 7-0 r ch ip sub-revision 0x01 0x04 t0_t4_ms_sts 1-0 r indicates master/slave state 0x05 t0_slave_phase_adj 11-0 r/w adjust t0 slav e phase from 0 ~ 409.5 ns in 0.1 ns steps 0x07 t4_slave_phase_adj 11-0 r/w adjust t4 slav e phase from 0 ~ 409.5 ns in 0.1 ns steps 0x09 fill_rate 3-0 r/w leaky buc ket fill rate, 1 ~ 16 ms 0x0a leak_rate 3-0 r/w leaky bucket leak rate, 1/n th of fill rate, n = 1 ~ 16 0x0b bucket_size 5-0 r/w leaky bucket size, 0 ~ 63 0x0c assert_threshold 5-0 r/w leaky bucket alarm assert threshold, 0 ~ 63 0x0d de_assert_threshold 5-0 r/w leaky bucke t alarm de-assert threshold, 0 ~ 63 0x0e freerun_cal 10-0 r/w freerun calibration of the tcxo, - 102.4 ~ + 102.3 ppm 0x10 disqualification_range 9-0 r/w referenc e disqualification range, 0 ~ 102.3 ppm 0x12 qualification_range 9-0 r/w reference qualification range, 0 ~ 102.3 ppm 0x14 qualification_timer 5-0 r/w refer ence qualification timer, 0 ~ 63 s 0x15 ref_selector 3-0 r/w determines which re ference data is shown in register 0x16 0x16 ref_frq_offset 14-0 r reference frequency and frequency offset are shown in bits 14-12 and 11-0 0x18 refs_activity 13-0 r referenc e and cross reference activity 0x1a refs_qual 11-0 r reference 1 ~ 12 qualification 0x1c t0_control_mode 5-0 r/w oop -follow/don?t follow, manual/auto, revertive, ho_usage, phasealignmode 0x1d t0_bandwidth 4-0 r/w bandwidth selection 0x1e t0_auto_active_ref 3-0 r indicates automatically selected reference 0x1f t0_manual_active_ref 3-0 r/w selects t he active reference in manual mode 0x20 reserved 31-0 r reserved 0x24 t0_long_term_accu_history 31-0 r long term accumulated history for t0 relative to the tcxo 0x28 t0_short_term_accu_history 31-0 r short term ac cumulated history for t0 relative to the tcxo 0x2c t0_user_accu_history 31-0 r/w user hol dover data for t0 relative to the tcxo 0x30 t0_ho_bw_ramp 7-0 r/w bits7-4, long term history accumuation bandwidth: 9.7, 4.9, 2.4, 1.2, 0.61, 0.03 mhz bits3-2, short term history accumulation bandwidth: 2.5, 1.24, 0.62, 0.31 mhz bit21:0, ramp control: none, 1, 1.5, 2 ppm/s 0x31 t0_priority_table 47-0 r/w ref1-12 selection priority for automatic mode, 4 bits/reference 0x37 t0_pll_status 7-0 r lth avail, lt h complete, oop, lol, los, sync 0x38 t0_accu_flush 0-0 w 0: flush current history, 1: flush all histories 0x39 t4_control_mode 5-0 r/w oop -follow/don?t follow, manual/auto, revertive, ho_usage, phasealignmode 0x3a t4_bandwidth 4-0 r/w bandwidth selection 0x3b t4_auto_active_ref 3-0 r indicates automatically selected reference 0x3c t4_manual_active_ref 3-0 r/w selects t he active reference in manual mode 0x3d reserved 31-0 r reserved 0x41 t4_long_term_accu_history 31-0 r long term accumulated history for t4 relative to the tcxo
data sheet #: tm084 page 8 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet 0x45 t4_short_term_accu_history 31-0 r short term ac cumulated history for t4 relative to the tcxo 0x49 t4_user_accu_history 31-0 r/w user hol dover data for t4 relative to the tcxo 0x4d t4_ho_bw_ramp 7-0 r/w bits7-4, long term history accumuation bandwidth: 9.7, 4.9, 2.4, 1.2, 0.61, 0.03 mhz bits3-2, short term history accumulation bandwidth: 2.5, 1.24, 0.62, 0.31 mhz bit21:0, ramp control: none, 1, 1.5, 2 ppm/s 0x4e t4_priority_table 47-0 r/w ref1-12 selection priority for automatic mode, 4 bits/reference 0x54 t4_pll_status 7-0 r lth avail, lt h complete, oop, lol, los, sync 0x55 t4_accu_flush 0-0 w 0: flush current history, 1: flush all histories 0x56 clk0_sel 0-0 r/w 155.52 mhz clock enable/disable for clk0 0x57 clk1_sel 1-0 r/w 19.44mhz/38.88mhz/77. 76mhz or disable select for clk1 0x58 clk2_sel 1-0 r/w 19.44mhz/38.88mhz/77. 76mhz or disable select for clk2 0x59 clk3_sel 5-0 r/w 8khz output 50% duty cy cle or pulse width selection for clk3 0x5a clk4_sel 5-0 r/w 2khz output 50% duty cy cle or pulse width selection for clk4 0x5b clk5_sel 1-0 r/w ds3/e3 select for clk5 0x5c clk6_sel 3-0 r/w ds1 x n / e1 x n selector for clk6 0x5d clk7_sel 1-0 r/w ds1/e1 selector for clk7 0x5e intr_event 9-0 r/w interrupt event 0x60 intr_enable 9-0 r/w interrupt enable table 4: register map addr reg name bits type description
data sheet #: tm084 page 9 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet general description the STC4130 is an integrated single chip solution for the synchronous clock in sdh and sonet network elements. it?s highly integrated design implements all of the necessary reference selection, monitoring, dig- ital filtering, synthesis, and control functions. an external ocxo or tcxo at either 10 or 20 mhz com- pletes a system level solution (see functional block diagram, figure 1). the STC4130 includes two independent dplls (digital phase-locked loop) implementing the timing functions of t0 and t4. each may select one of 12 reference inputs as its acti ve reference. t0 provides 7 of the chip?s 8 clock outputs while t4 provides one clock output. both t0 and t4 provide a cross refer- ence output for master/slave applications. reference frequencies are autodected and may each be 8khz, 64khz, 1.544mhz, 2.048mhz, 19.44mhz, 38.88mhz, or 77.76mhz. each reference input is continuously monitored for activity and frequency offset. activity monitoring is implemented with a leaky bucket accumulato r with programmable fill and leak rates. frequency offset is determined relative to the digitally calibrated external ocxo/tcxo. a reference is designated as ?q ualified? if it is active and its frequency is within the programmed frequency offset range for a pre-programmed time. active references may be selected manually or automatically, individually selectable for t0 and t4. in manual mode, the active reference is selected under application control, independant of it?s qualification status. in automatic mode, the active reference is selected according to revertivity status, and each reference?s priority and qualification. reference priorities are individually programmable. t0 and t4 each have their own priority tables. while a current active reference is qualified, revertivity determines whether a higher priority qualified reference should be selected as the new active reference. if revertivity is enabled, the highest priori ty qualified reference will always be selected as the active reference. if revertivity is not enabled, a new or returning qualified reference of higher priori ty will not be selected until the current active reference is disqualified. the two independent clock generators, t0 and t4, each include a dpll, which may operate in the freerun, synchronized, and holdover modes. both clock generators support master/slave operation for redundant applications. t0 generates connor- winfield?s proprietary synclink tm cross-couple data link, which provid es master/slave phase information and state data to ensure seamless side switches. t4 provides an 8k hz cross-couple signal. the slave output clock phase is user adjustable. the t0 and t4 clock generators may each be in fre- erun, synchronized, or holdover modes. in freerun, the clock outputs are simply determined by the accu- racy of the digitally calibrated ocxo/tcxo. in syn- chronized mode, the chip phase locks to the selected input reference. phase lock may be selected as arbi- trary or zero phase offset between the reference and clock outputs. all reference switches are performed in a hitless manner, and frequency ramp controls ensure smooth output signal transitions. when references are switched , the device will minimize phase transitions in the ou tput clocks. while synchro- nized, a frequency history is accumulated. in hold- over mode, the chip outputs are synthesized according to this or a user supplied history. the digital phase locked loop which provides the critical filtering and frequency/phase control functions is implemented with connor-winfield?s nova kernel - a set of well-proven algorithms and control that meet or exceed all requirements and lead the indus- try in critical jitter and accuracy performance parame- ters. filter bandwidth may be user configured. the device generates 8 independent synchronized output clocks. the first is at 155.52mhz. the second and third clocks may be programmed at 19.44/38.88/ 77.76mhz. the fourth and fifth are at 8khz and 2khz. the sixth is programmable at 1, 2, 4, 8, or 16 x t1 or e1. the seventh is programmable at either ds3 or e3. the eighth is programmable at either t1 or e1. control functions are provided either via a standard spi serial bus interface or 8-bit parallel bus register interfaces. these provide access to the STC4130?s comprehensive, yet simple to use internal control and status registers. para llel bus operation is sup- ported in the motorola mode, intel mode, or multiplex bus mode.
data sheet #: tm084 page 10 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet detailed description chip master clock input the device operates with an external ocxo or tcxo as its master clock, connected to the mclk input, pin 99. this may be at either 10 mhz or 20 mhz, mclk_frq_sel pin 98 = 0 for 10 mhz, 1 for 20 mhz. the external tcxo or ocxo may be calibrated, (thus calibrating the freerun output frequency of the chip) by writing an offset to the freerun_cal register, (0x0e/0f), from -102.4 to +102.3 ppm, in .1ppm steps, in two?s complement form. (see register descriptions section for details regarding register references in this section.) reference input monitoring and qualifi- cation the STC4130 accepts 12 external reference inputs at 8khz, 64khz, 1.544mhz, 2.048mhz, 19.44mhz, 38.88mhz, or 77.76mhz. input frequencies are detected automatically. the autodetected frequency of any reference may be read by selecting the refer- ence in the ref_selector register (0x15) and then reading the frequency from bits 4 - 6 of register ref_frq_offset (0x17). each input is monitored and qualified for activity and frequency offset. activity monitoring is accomplished with a leaky bucket accumulation algorithm, as shown in figure 2. the ?leaky bucket? accumulator has a fill rate window that may be set from 1 to 16 ms, where any hit of signal abnormality (or multiple hits) during the window increments the bucket count by one. the leak rate is 1/n th of the fill rate, where n may be set from 1 to 16, co rresponding to a leak rate window n x the fill rate wi ndow size. the leaky bucket accumulator decrements by one for each leak rate window that passes with no signal abnormality. both windows operate in a consecutive, non-overlapping manner. the bucket accumulator has alarm assert and alarm de-assert thresholds that can each be pro- grammed from 0 to 63. the fill rate is written to the fill_rate register, 0x09, and the leak rate is written to register leak_rate , 0x0a. the bucket size is written to register bucket_size (0x0b). the alarm assert threshold is written to register assert_threshold (0x0c), and the de-assert threshold is written to register de_assert_threshold (0x0d). bucket size must be greater than or equal to the alarm assert threshold value, and the alarm assert threshold value must be greater than the alarm de- assert value. alarms appear in the refs_activity register (0x18/ 19). a ?1? indicates activi ty, and a ?0? indicates an alarm, no activity. note that if a reference is active and returns at a different autodetected frequency, it will be become inactive immediately. figure 2: activity monitor reference inputs are also monitored and qualified for frequency offset. a pll qualification range may be programmed up to +/-102.3 ppm by writing to register qualification_range (0x12/13), and a disqualifica- tion range set up to +/-102.3 ppm, by writing to regis- ter disqualification_range (0x10/11). the qualification range must be set less than the disquali- fication range. additionally, a qualification timer may be programmed from 0 to 63 seconds by writing to register qualification_timer (0x14). the pll pull-in range is the same as the disqualification range. the actual frequency offset (relative to the calibrated ocxo/tcxo) of any reference may be read by selecting the reference in the ref_selector register (0x15) and then reading the offset value in bits 7 - 0/ 3 - 0 of register ref_frq_offset (0x16/17). figure 3 shows the reference qualification scheme. a reference is qualified if it has no activity alarm and is within the qualification range for more than the quali- fication time. an activity alarm or frequency offset frequency detector 8khz 64khz 1.544mhz 2.048mhz 19.44mhz 38.88mhz 77.76mhz leaky bucket accumulator bucket size: 0 ~ 63 leak rate 1/n th fill rate n = 1 ~ 16 fill rate 1ms ~ 16ms pulse monitor ref alarm assert threshold: 0 ~ 63 alarm de-assert threshold: 0 ~ 63
data sheet #: tm084 page 11 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet beyond the disqualificatio n range will disqualify the reference. it may then be re-qualified and the activity alarm is de-asserted, if it is within the qualification range for more than the qualification time. the reference qualification status of each reference may then be read from register refs_qual (0x1a/ 1b). figure 3: reference qualification and disqualification dpll active reference selection the t0 and t4 clock generators may be individually operated in either manual or automatic input refer- ence selection mode. the mo de is selected via the t0(4)_control_mode registers. manual reference selection mode in manual reference selection mode, the user may select the reference. manual reference selection mode is selected by setting bit 4 of the t0_control_mode (0x1c) or t4_control_mode (0x39) register (for t0 or t4, respectively) to 0. the reference is selected by writing to bits 0 - 3 of the t0_manual_active_ref (0x1f) and t4_manual_active_ref (0x3c) registers. automatic reference selection mode in automatic reference selection mode, the device will select one pre-qualifie d reference as the active reference. automati c reference selection mode is set by writing bit 4 of the t0_control_mode (0x1c) or t4_control_mode (0x39) register (for t0 or t4, respectively) to 1. the reference is picked according to its indicated pri- ority in the reference priority table, registers t0_priority_table (0x31~0x36) or t4_priority_table (0x4e ~ 0x0x53). each reference has one entry in the table, which may be set to a value from 0 to 15. ?0? ma sks-out the reference, while 1 to 15 set the priority, where ?1? has the highest, and ?15? has the lowest priority. the highest priority pre- qualified reference is chosen as the active reference. the automatically selected reference for each dpll may be read from registers t0_auto_active_ref (0x1e) and t4_auto_active_ref (0x3b). the pre-qualification scheme is described in the ref- erence inputs monitoring and qualification sec- tion. when a selected active reference is disqualified, the highest priority qualified remaining reference is chosen. if multiple references share the same priority, they are ordered according to the dura- tion of their qualification. the longer the duration, the higher the priority is set. when a reference is disqualified, and subsequently re-qualified as the highest priority candidate, it may or may not be re-selected as the active reference. this is determined by either enabling or disabling ?reversion? by writing bit 3 of the t0_control_mode (0x1c) or t4_control_mode (0x39) register (for t0 or t4, respectively) to ?1? for revertive or to ?0? for non-revertive operation. if reversion is enabled, a qualified/re-q ualified refer- ence will be selected as the new active reference, if it is the highest priority qualif ied reference at that time. if reversion is disabled, the active reference will not be pre-empted by a higher priority reference until it is disqualified. digital phase locked loop general description the STC4130 includes both a t0 and t4 clock gen- erator. each clock generator has a dpll, including a phase detector and a digital filter. each dpll may select any of the 12 input reference clocks in master mode. in slave mode, they will activity not good activity good qualified activity alarm asserted activity alarm asserted activity alarm de-asserted out of disqualification range within offset qualification range for more than qualification time
data sheet #: tm084 page 12 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet select the (t0/t4)_xsync_in cross-couple syn- clink tm data link(s) as the source of phase informa- tion. in master mode, the t0 and t4 clock generators may each operate in the freerun, synchronized, or hold- over modes: 1. free run in freerun mode, the clk(0-7) clock outputs are determined directly from and have the accuracy of the digitally calibrated free running ocxo/tcxo. reference inputs continue to be monitored for signal presence and frequency offset, but are not used to synchronize the outputs. 2. synchronized the clk(0-7) clock outputs are phase locked to and track the selected input reference. upon entering the locking mode, the device begins an acquisition pro- cess that includes reference qualification and fre- quency slew rate limiting, if needed. once satisfactory lock is achieved, the ?locked? state is entered, and the ?sync? bit is set in the t(0/ 4)_dpll_status register. each dpll?s loop bandwidth may be set indepen- dently. loop bandwidth is selectable from 90mhz to 107hz, by writing to the t0/4_bandwidth registers (0x1d/0x3a). 3. holdover upon entering holdover mode, the clk(0-7) clock outputs are determined from the holdover history established for the last selected reference, or from a user supplied holdover history. output frequency is determined by a weighted average of the holdover history, and accuracy is determined by the ocxo/ tcxo. holdover mode may be entered manually or automatically. automatic entry into holdover mode occurs when operating in the automatic mode, the reference is lost, and no other valid reference exists. the transfer into and out of holdover mode is designed to be smooth and free of hits. figure 4 shows the phase lock loop states and transi- tions for operation with automatic reference selection in master mode. figure 4: device phase lock operational mode transi- tion in automatic refern ce selection/master mode dpll operating mode details the t0 and t4 clock generators may operate in the freerun, synchronized, or holdover modes, includ- ing some variants thereof: freerun mode the clk(0-7) clock outputs are synthesized using the free running ocxo/tcxo, calibrated with the freerun frequency offset. the calibration offset may be programmed by the application by writing to the freerun_cal register, (0x0e/0f). the calibration off- set may be programmed from -102.4 to +102.3 ppm, in .1ppm steps, in two?s complement form. the freerun mode may be entered automatically, when in the automatic refe rence selection mode (as shown in figure 4), or manually, by writing to the t(0/ 4)_manual_active_ref registers. locking locked holdover freerun synchronized frequency locked no reference available and ho available any reference available any reference available no reference available and ho not available active reference not available or higher priority reference is available in revertive mode
data sheet #: tm084 page 13 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet synchronized mode the synchronized mode may be entered automati- cally, when in the automa tic reference selection mode (as shown in figure 4), or manually, by writing to the t(0/4)_manual_active_ref registers (0x1f/ 0x3c), selecting a reference as well as the operating mode. each dpll?s loop bandwidth may be set indepen- dently. loop bandwidth is selectable from 90mhz to 107hz by writing to the t(0/4)_bandwidth registers (0x1d/ 0x3a). in the ?synchronized? mode, bit 0 of the t(0/ 4)_control_mode registers (0x1c, 0x39) deter- mines the output clock to input reference phase alignment mode. in ?arbitrary? mode, the clock output phase relationship relative to the reference input phase is according to the initial start-up phase. in ?phase align? mode, the ou tput clocks are phase aligned to the selected reference. (it should be noted that output-to-reference phase alignment is meaning- full only in those cases where the output frequency and reference are the same or related by a factor of 2 n .) when locked on an external reference, two holdover histories are built, for use in holdover mode: 1) long-term history ? this is a long-term averaged frequency of the selected external reference, accumulated according to a sin- gle-pole low pass filtering algorithm. the - 3db point of the algorithm may be applica- tion programmed for 9.7, 4.9, 2.4, 1.2, 0.61, or 0.30 mhz, by writing to the t(0/ 4)_ho_ramp registers (0x30/ 0x4d). inter- nally, an express mode is used initially to apply a lower time-constant to speed up the history accumulation process. when a long term history has been built, it is indicated as available by the lha bit 7 of the t(0/ 4)_dpll_status registers (0x37/0x54). additionally, the application may flush/rebuild this long-term history, by writing to the t(0/ 4)_accu_flush registers (0x38, 0x55). the long-term history is used when operating in holdover mode, and may be read from the t(0/4)_long_term_accu_history regis- ters (0x24-0x27/ 0x41-0x44). 2) short-term history ? the short term history may be programmed for a -3db point of 2.5, 1.24, 0.62, or 0.31 mhz by writing to the t(0/ 4)_ho_ramp registers (0x30/ 0x4d). the short-term history is used, in the event of a reference loss in manual reference selection mode, and may be read from the t(0/4)_short_term_accu_history regis- ters (0x28-0x2b/ 0x45-ox48) in manual mode selection, there are two special cases of the synchronized mode: a) ?zombie? mode ? if the selected active reference signal is lost, the dpll output is generated according to a short-term history. b) out of pull-in range mode - if the selected refer- ence exceeds the pull-in range as programmed by the application, the dpll output may be pro- grammed to stay at the pull- in range limit, or to follow the reference. this is programmed by writing to bit 5 of the t(0/4)_control_mode registers (0x1c/ 0x39), specifying whether to follow or not follow a reference that has exceded the pull-in range. additionally, when a device is operated as a slave in a master/slave pair (by tying the t(0/4)_m/s pin low), the device locks and phase align on the cross-cou- pled synclink tm data link signal on the (t0/ t4)_xsync_in input. when the device has locked on a reference, the ?sync? bit 0 is set in the t(0/4)_dpll_status regis- ter (0x37/ 0x54). if synchronization is lost, the ?lol? bit 2 is set in the t(0/4)_dpll_status register. holdover mode the application may select either of two sources of frequency offset in holdover mode, as determined by writing bit 2 of the t(0/4)_control_mode registers (0x1c/ 0x39): a) device accumulated history holdover mode ? uses the long-term hist ory accumulated by the device to synthesize the dpll output this is analo- gous to the freerun mode, except that the holdover algorithms effectively supply the ?frequency offset? from the holdover history. b) user supplied history mode ? the dpll output is synthesized according to an application supplied frequency offset, as provided in the t(0/ 4)_user_accu_history registers (0x2c/ 0x49). to facilitate the user?s accumulation of a holdover his- tory, the user may read the short term history of the active reference from the t(0/ 4)_shor_term_accu_history registers (0x28-0x2b/
data sheet #: tm084 page 14 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet 0x45-0x48). on either transition, from synchronized to holdover, or back from holdover to synchronized, an applica- tion programmable maximum slew rate of 1, 1.5, or 2 ppm/second (or no slew rate limit) is applied, as writ- ten to the t(0/4)_ho_ramp registers (0x30/ 0x4d). output clocks the clock output section includes 4 clock genera- tions, an apll, and four dividers, and generates nine synchronized clocks, as shown in figure 5. figure 5: output clocks the first synthesizer drives an analog pll and gen- erates five output clocks. it is driven from the t0 dpll: ? clk0 : 155.52 mhz (lvpecl), enabled/dis- abled by writing the clk0_sel register (0x56), bit 0. ? clk1 : programmable at 19.44mhz, 38.88mhz, 77.76 mhz, and ?disabled?, by writing to the clk1_sel register (0x57), bits 0 - 1. ? clk2 : programmable at 19.44mhz, 38.88mhz, 77.76 mhz, and ?disabled?, by writing to the clk2_sel register (0x58), bits 0 - 1. ? clk3 : 8khz, 50% duty cycle or programma- ble pulse width, and may be disabled by writ- ing to the clk3_sel register (0x59), bits 0 - 5. ? clk4 : 2khz, 50% duty cycle or programma- ble pulse width, and may be disabled by writ- ing to the clk4_sel register (0x5a), bits 0 - 5. two synthesizers generate additional clocks from the t0 clock generator: ? clk5 : either ds3 or e3 rate, or ?disabled?, programmed by writing to the clk5_sel reg- ister (0x5b), bits 0 - 1. ? clk6 : programmable at nxds1 or nxe1 where n=1,2,4,8,16, or may be disabled, by writing to the clk6_sel register (0x5c), bits 0 - 3. one synthesizer is driven by the t4 clock generator: ? clk7 : either ds1 or e1 rate, or ?disabled?, programmed by writing to the clk7_sel reg- ister (0x5d), bits 0 - 1. when a clock output is disabled, the pin is tri-stated. in addition, the t0_xsync_out and t4_xsync_out outputs provide phase information and state data for master/slave operation of the t0 and t4 clock generators. note that the clk1, 2, 5 and 6 are phase aligned with the clk3 (8khz) as shown in figure 7. clk3 is phase aligned with clk4 (2khz). t0 dpll t4 dpll clk apll divider divider divider divider clk1 clk2 clk3 clk4 clk0 clk7 clk6 clk5 t1, e1 ds3, e3 n xds1, n xe1 n = 1,2,4,8,16 155.52 mhz 19.44 / 38.88 / 77.76 mhz 19.44 / 38.88 / 77.76 mhz 8 khz 2 khz generation clk generation clk generation clk generation
data sheet #: tm084 page 15 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet master/slave configuration pairs of STC4130 devices may be operated in a master/slave conf iguration for adde d reliability, as shown in figure 6. figure 6: master/slave configuration devices are configured for master/slave operation by cross-connecting their respective t(0/4)_xsync_out and/or t(0/4)_xsync_in pins. the t(0/4)_ms pins determine the master or slave mode for each clock generator. 1=master, 0=slave. thus, master/slave state is always manually con- trolled by the application. the master synchronizes to the selected input reference, while the slave syn- chronizes and phase-aligns according to data received over the t(0/4)_xsync_out / t(0/ 4)_xsync_in data link from the unit in master mode. the t0 and t4 pll?s may be operated completely independent of each other ? either or both may be cross-connected as master/slave pairs across two STC4130 devices, and master/slave states may be set the same or opposite within a given device. in slave mode, the operational mode is ?synchro- nized? and the t(0/4)_xsync_out data links provide phase and state information. bits 0 and 1 of the t0_t4_ms_sts register reflect the states of the t(0/4)_ms pins. master/slave operation perfect phase alignment of the clk(x) output clocks (between the clock generators in two devices) would require no delay on the cross-couple data link con- nection. to accommodate path length delays, the STC4130 provides a programmable phase skew fea- ture. see figures 7 and 8. the slave?s clk(x) outputs may be phase shifted from 0 to +409.5ns, in 100ps increments according to the contents of the t(0/ 4)_slave_phase_adj (0x05/06, 0x07/08) registers to compensate for the path length of the t(0/ 4)_xsync_out to t(0/4)_xsync_in connections. this offset may therefore be programmed to exactly compensate for the actual path length delay associ- ated with the particular application's cross-couple traces. thus, master/slave switches with the STC4130 devices may be accomplished with near- zero phase hits. the first time a clock generator becomes a slave, such as immediately after power-up, its output clock phase starts out arbitrar y, and will quickly phase- align to the master unit. the phase skew will be elim- inated (or converged to the programmed phase off- set) step by step. the whole pull-in-and-lock process will complete in about 16 se conds. there is no fre- quency slew protection in slave mode. in slave mode, the unit's mission is to lock to and follow the master. figure 7: t0 clk1-6 phase alignment and master/ slave skew control note the phase alignment of all clock outputs from the t0 clock generator with the 2khz output. t0 pll t4 pll STC4130 t0 pll t4 pll STC4130 t0_xsync_out t0_xsync_in t4_xsync_out t4_xsync_in t0_ms t4_ms t4_ms t0_ms master t0 clock generator STC4130 slave t0 clock generator STC4130 2khz 8khz 38.88mhz 77.76mhz t1/e1 t3/e3 2khz 8khz 38.88mhz 77.76mhz t1/e1 t3/e3 programmable skew 0 to 409.5 ns
data sheet #: tm084 page 16 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet figure 8: t4 clk7 master/slave skew control once a pair of clock generators has been operating in aligned master/slave mode, and a master/slave switch occurs, the clock generator that becomes master will maintain its ou tput clock phase and fre- quency while a phase rebuild (to the current output clock phase) is performed on its selected reference input. therefore, as master mode operation com- mences, there will be no phas e or frequency hits on the clock output. assuming the phase offset is pro- grammed for the actual propagation delay of this cross-couple path, there will again be no phase hits on the output clock of th e clock generator that has transitioned from master to slave. the data link will also provide state inform ation that will allow the new master to lock on the same reference as the old mas- ter. master t4 clock generator STC4130 slave t4 clock generator STC4130 t1/e1 t1/e1 programmable skew 0 to 409.5 ns
data sheet #: tm084 page 17 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet processor interface descriptions the STC4130 supports four common microprocessor cont rol interfaces: spi, motoro la, intel, and multiplex parallel. the control interfac e mode is selected with the bus_mode(0/1) pins: the following sections describe each bus mode?s interface timing: spi bus mode the spi interface bus mode uses the bus_cs , bus_ale, bus_wrb, and bus_ rdy pins, corresponding to cs, sclk, sdi, and sdo respectively, wit h timing as shown in figures 9 and 10: serial bus timing figure 9: serial bus timing, read access figure 10: serial bus timing, write access bus_mode1, bus_mode0 bus mode 00 spi 01 motorola 10 intel 11 multiplex parallel a0 cs sclk sdi 1 2 3 4 a6 a5 a4 a3 a2 a1 5 6 7 8 13 14 15 16 9 10 11 12 0 d7 lsb msb sdo msb lsb t drdy t ch t cl t cs t ds t dh t csmin t dhld d6 d5 d4 d3 d2 d1 d0 t cshld t cstri cs sclk sdi t ds 1 2 3 4 a6 a5 a4 a3 a2 a1 a0 5 6 7 8 13 14 15 16 9 10 11 12 1 t dh lsb msb t ch t cl t cs d7 d6 d5 d4 d3 d2 d1 d0 lsb msb t csmin t cshld
data sheet #: tm084 page 18 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet table 5: serial bus timing symbol description min max unit t cs cs low to sclk high 10 ns t ch sclk high time 25 ns t cl sclk low time 25 ns t ds data setup time 10 ns t dh data hold time 10 ns t drdy data ready 7 ns t dhld data hold 5 ns t cshld chip select hold 30 ns t cstri chip select to data tri-state 5 ns t csmin minimum delay between successive accesses 50 ns
data sheet #: tm084 page 19 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet motorola bus in motorola mode, the device will in terface to 680xx type processors. the bus_cs, bus_rdb, bus_a(6-0), bus_ad(7-0), and bus_rdy pi ns are used, corresponding to cs, r/w, a, ad, and rdy, respectively. timing is as follows: motorola bus timing figure 11: motorola bus read timing table 6: motorola bus read timing symbol description min max unit t cs cs low time 50 ns t csd cs minimum high time between reads/writes 50 ns t rws read/write setup time 0 ns t rwh read/write hold time 0 ns t as address setup 10 ns t ah address hold 0 ns t dd1 data valid delay from cs low 50 ns t dd2 data high-z delay from cs low 10 ns t rdy1 cs low to rdy high delay 13 ns t rdy rdy high time 37 50 ns t rdyh cs hold after rdy low 0 ns cs t rws t dd1 t cs r/w a ad rdy t csd t rwh t as t ah address data t dd2 t rdyd1 t rdyd2 t rdyh t rdy
data sheet #: tm084 page 20 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet figure 12: motorola bus write timing table 7: motorola bus read timing t rdy2 rdy high-z delay after cs high 9 ns symbol description min max unit t cs cs low time 50 ns t csd cs minimum high time between writes/reads 50 ns t rws read/write setup time 0 ns t rwh read/write hold time 0 ns t as address setup 10 ns t ah address hold 0 ns t ds data setup time before cs high 10 ns t dh data hold time after cs high 10 ns t rdyd1 cs low to rdy high delay 13 ns t rdy rdy high time 37 ns t rdyh cs hold after rdy low 0 ns symbol description min max unit cs t rws t ds t cs r/w a ad rdy t csd t rwh t as t ah address data t dh t rdyd1 t rdyd2 t rdyh t rdy
data sheet #: tm084 page 21 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet intel bus in intel mode, the device will inte rface to 80x86 type processors. the bus_cs, bus_wrb, bus_rdb, bus_a(6-0), bus_ad(7-0), and bus_rdy pins are used, corresponding to cs, wrb, rdb, a, ad, and rdy, respectively. timing is as follows: figure 13: intel bus read timing table 8: intel bus read timing t rdyd2 rdy high-z delay after cs high 7 ns symbol description min max unit t rdbs read setup time 0 ns t rdb read low time 40 ns t rdbh read hold time 0 ns t rdb1 time between consecutive reads 50 ns t as address setup 10 ns t ah address hold 0 ns t dd1 data valid delay from rdb high 50 ns t dd2 data high-z delay from rdb high 10 ns t rdyd1 cs low to rdy high delay 13 ns symbol description min max unit cs t rdbs t dd1 wrb a ad rdy t rdb t as t ah address data t dd2 t rdyd2 t rdyd3 t rdyh t rdy rdb t rdb1 t rdbh t rdyd1
data sheet #: tm084 page 22 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet t rdyd2 rdb low to rdy low 40 ns t rdy rdy low time 50 ns t rdyh rdb hold after rdy high 0 ns t rdy3 rdy high-z delay after cs high 11 ns symbol description min max unit
data sheet #: tm084 page 23 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet figure 14: intel write read timing table 9: intel bus write timing symbol description min max unit t wrbs write setup time 0 ns t wrb write low time 40 ns t wrbh write hold time 0 ns t wrb1 time between consecutive writes 50 ns t as address setup 10 ns t ah address hold 0 ns t ds data setup time before cs high 10 ns t dh data hold time after cs high 10 ns t rdyd1 cs low to rdy high delay 13 ns t rdyd2 rdb low to rdy low 40 ns t rdy rdy low time 50 ns t rdyh rdb hold after rdy high 0 ns t rdy3 rdy high-z delay after cs high 10 ns cs t wrbs t ds wrb a ad rdy t wrb t as t ah address data t dh t rdyd2 t rdyd3 t rdyh t rdy rdb t wrb1 t wrbh t rdyd1
data sheet #: tm084 page 24 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet multiplex bus mode in multiplex bus mode, the device can interface with mi croprocessors which share the address and data on the same bus signals. the bus_ale , bus_cs , bus_wrb, bus_rdb, bus_ad(7 -0), and bus_rdy pins are used, corresponding to ale , cs, wrb, rdb, ad, and rdy, respectively. multiplex bus timing figure 15: multiplex bus read timing table 10: multiplex bus read timing symbol description min max unit t ale ale high time 10 ns t aled ale falling edge to rdb low 0 ns t ads address setup time 10 ns t adh address hold time 10 ns t css read setup time 0 ns t rdb read time 40 ns t csh cs hold time 0 ns t csd cs delay for multiple read/writes 50 ns t dd1 data valid delay from rdb low 50 ns t dh2 data high-z from rdb high 10 ns t rdyd1 cs low to rdy active 13 ns t rdyd2 rdb low to rdy low 40 ns t rdy rdy low time 50 ns t rdyh read hold after rdy high 0 ns cs t dd1 wrb ad rdy t rdb address data t dh2 t rdyd2 t rdyd3 t rdyh t rdy rdb t csd t csh t rdyd1 t css t aled t ale t ads t adh ale
data sheet #: tm084 page 25 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet figure 16: multiplex bus write timing table 11: multiplex bus write timing t rdyd3 rdy high-z delay after cs high 10 ns symbol description min max unit t ale ale high time 10 ns t aled ale falling edge to rdb low 0 ns t ads address setup time 10 ns t adh address hold time 10 ns t css write cs setup time 0 ns t wrb write time 40 ns t csh cs hold time 10 ns t csd cs delay for multiple write/reads 50 ns t ds data setup time 10 ns t dh data hold time 10 ns t rdyd1 cs low to rdy active 13 ns t rdyd2 wrb low to rdy low 40 ns t rdy rdy low time 50 ns t wrbh wrb hold after rdy high 0 ns t rdyd3 rdy high-z delay after cs high 9 ns symbol description min max unit cs t ds wrb ad rdy t wrb address data t dh t rdyd2 t rdyd3 t wrbh t rdy rdb t csd t csh t rdyd1 t css t aled t ale t ads t adh ale
data sheet #: tm084 page 26 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet register descriptions and operation general register operation the STC4130 device has 1, 2, and 4 byte registers. on e byte registers are read and written directly. two and four byte registers must be read and written in a specific manner and order, as follows: multibyte register reads a multibyte register read must commence with a read of th e least significant byte first. this triggers a transfer of the remaining byte(s) to a holdin g resgister, ensuring that the rema ining data will not change with the con- tinuing operation of the device. the remaining byte(s) ma y then be read in any order, and with no timing restric- tions. multibyte register writes a multibyte register write must comm ence with a write to the least signific ant byte first. subsequent writes to the remaining byte(s)must be performed in ascending byte order, but with no timing restrictions. multibyte reg- ister writes are temporarily stored in a holding register, and are transferred to the target register when the most significant byte is written. clearing bits in the interrupt status register interrupt event register ( intr_event , 0x5e~0x5f) bits are cleared by writin g a ?1? to the bit position to be cleared. interrupt bit positions to be left as is are written with a ?0?. default register settings chip_id, 0x00 (r) chip_rev, 0x02 (r) chip_sub_rev, 0x03 (r) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 0x30 0x01 0x41 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x02 0x01 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x03 0x01
data sheet #: tm084 page 27 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet t0_t4_ms_sts, 0x04 (r/w) reflects the states of the t0/t4_master_slave select pins. 1 = master, 0 = slave t0_slave_phase_adj, 0x05 (r/w) the t0 slave phase may be adjusted 0 to 409.5 ns rela tive to the cross couple input with 0.1 ns resolution. this is a 12 bit register, split across address 0x05 and 0x06. default value: 0. t4_slave_phase_adj, 0x07 (r/w) the t4 slave phase may be adjusted 0 to 409.5 ns rela tive to the cross couple input with 0.1 ns resolution. this is a 12 bit register, split across address 0x07 and 0x08. default value: 0. fill_rate, 0x09 (r/w) sets the fill rate window size for the referenc e activity monitor. the value can be set from 0 to 15, correspond- ing to 1ms to 16ms. default value: 1. leak_rate, 0x0a (r/w) sets the leak rate for the re ference activity monitor to 1/ nth of the fill rate, correspond ing to n x the fill rate win- dow size. valid values from 0 to 15, co rresponding to n = 1 to 16. for example, if the fill rate is set to 4ms and the leak rate is set to 3 (n = 4), the leak rate window size will be 16ms. default value: 3. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x04 not used t4 m/s t0 m/s address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x05 adjust t0 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, lower 8 bits 0x06 not used adjust t0 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, upper 4 bits address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x07 adjust t4 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, lower 8 bits 0x08 not used adjust t4 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, upper 4 bits address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x09 not used leaky bucket fill rate window, 0 ~ 15, default = 0 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0a not used leak rate, 1/n th of fill rate, 0 ~ 15
data sheet #: tm084 page 28 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet bucket_size, 0x0b (r/w) sets the leaky bucket size for the refe rence activity monitor. bucket size mu st be greater than or equal to the alarm assert value. invalid values will not be written to the register. default value: 20. assert_threshold, 0x0c (r/w) sets the leaky bucket alarm assert threshold for the re ference activity monitor. the alarm assert threshold value must be greater than the de-assert threshold value and less than or equal to the bucket size value. invalid values will not be written to the register. default value: 15. de_assert_threshold, 0x0d (r/w) sets the leaky bucket alarm de-assert threshold for th e reference activity monitor. the de-assert threshold value must be less than the assert threshold value. invalid values will not be wr itten to the register. default value: 10. freerun_cal, 0x0e (r/.w) freerun tcxo/ocxo calibration, from -102.4 to +102.3 ppm, in .1ppm steps, two?s complement. default value: 0. disqualification_range, 0x10 (r/w) reference disqualification range, from 0 to +102.3 ppm, in 0.1 ppm steps. this also sets the pull-in range, beyond which, in manual mode, a re ference will either not be synchroniz ed to or no longer will be followed (depending on the state of the oop bits in the t0/4_control_mode registers). default value: 110. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0b not used leaky bucket size, 0 ~ 63 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0c not used leaky bucket alarm assert threshold, 0 ~ 63 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0d not used leaky bucket alarm de-assert threshold, 0 ~ 63 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x0e lower 8 bits 0x0f not used upper 3 bits address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x10 lower 8 bits 0x11 not used upper 3 bits
data sheet #: tm084 page 29 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet qualification_range, 0x12 (r/w) reference qualification range, from 0 to +102.3 ppm, in 0.1 ppm steps. default value: 100. qualification_timer, 0x14 (r/w) reference qualification timer, from 0 to 255 s. default value: 10. ref_selector, 0x15 (r/w) determines which refe rence data is displayed in register 0x16 and 0x17. valid values from 1 to 12. default value: 1. ref_frq_offset, 0x16 (r) displays the frequency offset and reference frequency for the reference selected by the ref_selector (0x15) register. frequency offset is from -204.8 to +204.7 ppm in 0.1 ppm steps, two?s complement. the reference fre- quency is determined as follows: refs_activity, 0x18 (r) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x12 lower 8 bits 0x13 not used upper 3 bits address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x14 0 ~ 63 s address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x15 not used 1 ~ 12 (0x1 ~ 0xc) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x16 lower 8 bits of frequency offset 0x17 not used reference frequency up per 4 bits of frequency offset 0x13, bits 6 ~ 4 frequency 000 no signal 001 8 khz 010 64 khz 011 1.544 mhz 100 2.048 mhz 101 19.44 mhz 110 38.88 mhz 111 77.76 mhz address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x18 ref 8 ref 7 ref 6 ref 5 ref 4 ref 3 ref 2 ref 1 0x19 not used t4_xsync_in t0_xsync_in ref 12 ref 11 ref 10 ref 9
data sheet #: tm084 page 30 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet reference activity indicator, 0 = no activity, 1 = activity. refs_qual, 0x1a (r) reference qualification indicator, 0 = not qualified, 1 = qualified. t0_control_mode, 0x1c (r/w) mode control bits for t0. bit 0: 0 = arbitrary (use initial phase), 1 = phase align bit 2, accu_usage: 0 = device calculated long term hist ory (lth) is used; 1 = user supplied history is used. bit 5, oop: in manual mode, when the selected active refe rence is out of the pull-in range, as specified in reg- ister disqualification_range , 0x10, oop will determine if th e reference is to be follo wed, 0 = don?t follow, 1 = follow. default value: 0. t0_bandwidth, 0x1d (r/w) sets the t0 bandwidth: address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x1a ref 8 ref 7 ref 6 ref 5 ref 4 ref 3 ref 2 ref 1 0x1b not used ref 12 ref 11 ref 10 ref 9 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x1c not used oop: out of pull-in range: 0=follow 1=don?t fol- low manual/ auto 0=manual 1=auto revertive 0=non- revertive 1=rever- tive accu_usage 0=lth 1=user phase align mode 0=arbitrary 1=align address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x1d not used 0x1d, bits 4 ~ 0 bandwidth, hz 0 107 150 224 312 45.9 52.9 61.5 7.73 80.37
data sheet #: tm084 page 31 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet default value: 6. t0_auto_active_ref, 0x1e (r) indicates the automatically selected active reference for t0, when the device is a ?master?. when the device is a ?slave?, the mate?s active reference is indicated. t0_manual_active_ref, 0x1f (r/w) selects the active reference and the phase align mode for t0 in manual reference select mode. default value: 0. t0_long_term_accu_history, 0x24 (r) long term accumulated histor y for t0 relative to the tcxo. resolution is 0.745x10 -3 ppb. t0_short_term_accu_history, 0x28 (r) short term accumulated history for t0 rela tive to the tcxo. resolution is 0.745x10 3 ppb. 90.18 10 0.09 31 ~ 11 reserved address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x1e not used values from 0 - 12 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x1f not used values from 0 - 15 bit 3 ~ bit 0 phase align mode/ref selection 0000 freerun 0001 ~ 1100 ref 1 ~ ref 12 1101 ~ 1111 holdover address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x24 bits 0 - 7 of 32 bit long term holdover history 0x25 bits 8 - 15 of 32 bit long term holdover history 0x26 bits 16 - 23 of 32 bit long term holdover history 0x27 bits 24 - 31 of 32 bit long term holdover history address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x28 bits 0 - 7 of 32 bit short term holdover history 0x29 bits 8 - 15 of 32 bit short term holdover history 0x2a bits 16 - 23 of 32 bit short term holdover history 0x2b bits 24 - 31 of 32 bit short term holdover history 0x1d, bits 4 ~ 0 bandwidth, hz
data sheet #: tm084 page 32 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet t0_user_accu_history, 0x2c (r/w) user accumulated history for t0 relative to the tcxo. resolution is 0.745x10 -3 ppb. default value: 0. t0_ho_ramp, 0x30 (r/w) holdover bandwidth and ramp controls for t0: default value: 0x26 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x2c bits 0 - 7 of 32 bit user holdover history 0x2d bits 8 - 15 of 32 bit user term holdover history 0x2e bits 16 - 23 of 32 bit user term holdover history 0x2f bits 24 - 31 of 32 bit user term holdover history address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x30 not used long term history bandwidth short term history abdn- width ramp control 0x30, bits 6 ~ 4 long term history bandwidth, mhz 000 9.7 mhz 001 4.9 mhz 010 2.4 mhz 011 1.2 mhz 100 0.61 mhz 101 0.30 mhz 0x30, bits 3 ~ 2 short term history bandwidth, mhz 00 2.5 mhz 01 1.24 mhz 10 0.62 mhz 11 0.31 mhz 0x30, bits 1 ~ 0 ramp control, ppm/sec 00 no control 01 1 10 1.5 11 2
data sheet #: tm084 page 33 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet t0_priority_table, 0x31 (r/w) reference priority for automatic reference selection mode. lower values have higher priority: default value: 0. t0_pll_status, 0x37 (r) sync: indicates synchronization has been achieved los: loss of signal lol: loss of lock oop: out of pull-in range lhc: long term history complete lha: long term history available t0_accu_flush, 0x38 (w) writing to this register will perform a flush of the accumulated history. the value of bit zero determines which histories are flushed. bit 0 = 0, flush t0 current history only; bit 0 = 1, flush all t0 histories. t4_control_mode, 0x39 (r/w) address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x31 ref 2 priority ref 1 priority 0x32 ref 4 priority ref 3 priority 0x33 ref 6 priority ref 5 priority 0x34 ref 8 priority ref 7 priority 0x35 ref 10 priority ref 9 priority 0x36 ref 12 priority ref 11 priority 0x31 - 0x36, 4 bits reference priority 0000 disable reference 0001 ~ 1111 1 ~ 15 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x37 lha 1=available 0=not available lhc 1=com- plete 0=not com- plete reserved oop 1=out of pull-in range 0=in range lol 0=no lol 1=lol los 0=no los 1=los sync: 0=no sync 1=sync address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x38 not used ho flush address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x39 not used oop: out of pull-in range: 0=follow 1=don?t fol- low manual/ auto 0=manual 1=auto revertive 0=non- revertive 1=rever- tive accu_usage 0=lth 1=user phase align mode 0=arbitrary 1=align
data sheet #: tm084 page 34 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet mode control bits for t4. bit 0: 0 = arbitrary (use initial phase), 1 = phase align bit 2, accu_usage: 0 = device calculated long term hist ory (lth) is used; 1 = user supplied history is used. bit 5, oop: in manual mode, when the selected active refe rence is out of the pull-in range, as specified in reg- ister disqualification_range , 0x10, oop will determine if th e reference is to be follo wed, 0 = don?t follow, 1 = follow. default value: 0. t4_bandwidth, 0x3a (r/w) sets the t4 bandwidth: default value: 0. t4_auto_active_ref, 0x3b (r) indicates the automatic select ed active reference for t4. t4_manual_active_ref, 0x3c (r/w) selects the active reference and the phase align mode for t4 in manual reference select mode. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x3a not used 0x1d, bits 4 ~ 0 bandwidth, hz 0 107 150 224 312 45.9 52.9 61.5 7.73 80.37 90.18 10 0.09 31 ~ 11 reserved address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x3b not used values from 0 - 12 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x3c not used values from 0 - 15 bit 3 ~ bit 0 phase align mode/ref selection 0000 freerun 0001 ~ 1100 ref 1 ~ ref 12
data sheet #: tm084 page 35 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet default value: 0. t4_long_term_accu_history, 0x41 (r) long term accumulated histor y for t4 relative to the tcxo. resolution is 0.745x10 -3 ppb. t4_short_term_accu_history, 0x45 (r) short term accumulated history for t4 rela tive to the tcxo. resolution is 0.745x10 -3 ppb. t4_user_accu_history, 0x49 (r/w) user accumulated history for t4 relative to the tcxo. resolution is 0.745x10 -3 ppb. default value: 0. t4_ho_ramp, 0x4d (r/w) holdover bandwidth and ramp controls for t4: 1101 ~ 1111 holdover address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x41 bits 0 - 7 of 32 bit long term holdover history 0x42 bits 8 - 15 of 32 bit long term holdover history 0x43 bits 16 - 23 of 32 bit long term holdover history 0x44 bits 24 - 31 of 32 bit long term holdover history address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x45 bits 0 - 7 of 32 bit short term holdover history 0x46 bits 8 - 15 of 32 bit short term holdover history 0x47 bits 16 - 23 of 32 bit short term holdover history 0x48 bits 24 - 31 of 32 bit short term holdover history address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x49 bits 0 - 7 of 32 bit user holdover history 0x4a bits 8 - 15 of 32 bit user term holdover history 0x4b bits 16 - 23 of 32 bit user term holdover history 0x4c bits 24 - 31 of 32 bit user term holdover history address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x4d not used long term history bandwidth short term history band- width ramp control 0x30, bits 6 ~ 4 long term history bandwidth, mhz 000 9.7 mhz 001 4.9 mhz 010 2.4 mhz bit 3 ~ bit 0 phase align mode/ref selection
data sheet #: tm084 page 36 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet default value: 0x24. t4_priority_table, 0x4e (r/w) reference priority for automatic reference selection mode. lower values have higher priority: default value: 0. t4_pll_status, 0x54 (r) 011 1.2 mhz 100 0.61 mhz 101 0.30 mhz 0x30, bits 3 ~ 2 short term history bandwidth, mhz 00 2.5 mhz 01 1.24 mhz 10 0.62 mhz 11 0.31 mhz 0x30, bits 1 ~ 0 ramp control, ppm/sec 00 no control 01 1 10 1.5 11 2 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x4e ref 2 priority ref 1 priority 0x4f ref 4 priority ref 3 priority 0x50 ref 6 priority ref 5 priority 0x51 ref 8 priority ref 7 priority 0x52 ref 10 priority ref 9 priority 0x53 ref 12 priority ref 11 priority 0x31 - 0x36, 4 bits reference priority 0000 disable reference 0001 ~ 1111 1 ~ 15 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x54 lha 1=available 0=not available lhc 1=com- plete 0=not com- plete reserved oop 1=out of pull-in range 0=in range lol 0=no lol 1=lol los 0=no los 1=los sync: 0=no sync 1=sync 0x30, bits 6 ~ 4 long term history bandwidth, mhz
data sheet #: tm084 page 37 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet sync: indicates synchronization has been achieved los: loss of signal lol: loss of lock oop: out of pull-in range lhc: long term history complete lha: long term history available t4_accu_flush, 0x55 (w) writing to this register will perform a flush of the accumulated history. the value of bit zero determines which histories are flushed. bit 0 = 0, flush t4 current history only; bit 0 = 1, flush all t4 histories. clk0_sel, 0x56 (r/w) enables or disables the 155.52mhz clk0 output. default vale: 0. clk1_sel, 0x57 (r/w) selects or disables the clk1 output. default value: 1. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x55 not used ho flush address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x56 not used 0=disable 1=enable address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x57 not used clk1 select 0x57, bits 1 ~ 0 clk1 output 0 disabled 1 19.44mhz 2 38.88mhz 3 77.76mhz
data sheet #: tm084 page 38 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet clk2_sel, 0x58 (r/w) selects or disables the clk2 output. default value: 2. clk3_sel, 0x59 (r/w) selects or disables the clk3 output, and sets the pu lse width. in variable pulse width, the width may be selected from 1 to 62 times the period of the 155.52mhz output (~6.43ns to 399ns). default value: 63. clk4_sel, 0x5a (r/w) selects or disables the clk4 output, and sets the pu lse width. in variable pulse width, the width may be selected from 1 to 62 times the period of the 155.52mhz output (~6.43ns to 399ns). default value: 63. clk5_sel, 0x5b (r/w) selects or disables the clk5 output. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x58 not used clk2 select 0x58, bits 1 ~ 0 clk2 output 0 disabled 1 19.44mhz 2 38.88mhz 3 77.76mhz address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x59 not used clk3 select 0x59, bits 5 ~ 0 clk3 8khz output 0 disabled 1 ~ 62 pulse width 1 to 62 cycles of 155.52mhz 63 50% duty cycle address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x5a not used clk4 select 0x5a, bits 5 ~ 0 clk4 2khz output 0 disabled 1 ~ 62 pulse width 1 to 62 cycles of 155.52mhz 63 50% duty cycle address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x5b not used clk2 select 0x5b, bits 1 ~ 0 clk5 output 0 disabled
data sheet #: tm084 page 39 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet default value: 2. clk6_sel, 0x5c (r/w) selects or disables the clk6 output. default = 0110, 2.048mhz: default value: 1. clk7_sel, 0x5d (r/w) selects or disables the clk7 output. default value: 2. intr_event, 0x5e (r/w) 1ds3 2e3 3 disabled address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x5c not used clk6 select 0x5c, bits 3 ~ 0 clk6 output 0 disabled 1 2.048mhz 2 4.096mhz 3 8.192mhz 4 16.384mhz 5 32.768mhz 9 1.544mhz 10 3.088mhz 11 6.176mhz 12 12.352hz 13 24.704mhz address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x5d not used clk7 select 0x5d, bits 1 ~ 0 clk7 output 0 disabled 1t1 2e1 3 disabled address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x5e event 7: t4 cross reference changed from non- active to active event 6: t4 cross reference changed from active to non- active event 5: t4 dpll status changed event 4: t4 active reference changed in auto selec- tion mode event 3: t0 cross reference changed from non- active to active event 2: t0 cross reference changed from active to non- active event 1: t0 dpll status changed event 0: t0 active reference changed in auto selec- tion mode 0x5b, bits 1 ~ 0 clk5 output
data sheet #: tm084 page 40 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet interrupt event, 0 = no event, 1 = event occurred. interrupt 8 and 9 apply to the 12 reference inputs only. interrupts are cleared by writing ?1?s? to the bit positions to be cleared (see general register operation, clearing bits in the interrupt status register section). intr_enable, 0x60 (r/w) interrupt disable/enable, 0 = disable, 1 = enable. default value: 0. application notes this section describes typical application use of the st c4130 device. the general section applies to all appli- cation variations, while the remaining sections detail use depending on the level of control and automatic oper- ation the application desires. general power and ground well-planned noise-minimizing power and ground are essential to achieving the best performance of the device. the device requires 3.3 and 1.8v digital power a nd 1.8v analog power input. all digital i/o is at 3.3v, lvttl compatible. the 1.8v may originate from a commo n source but should be in dividually filtered and iso- lated, as shown in figure 17. alternatively, a separate 1.8v regulator may be used for the analog 1.8 volts. r/c filter components should be chosen for minimum induct ance and kept as close to the chip as possible. it is desirable to provide individual bypass capacitors, located close to the chip, for each of the digital power input leads, subject to board space and layout constraints. on power-up, it is desirable to have the 1.8v either lead or be coincident with, but not lag the application of 3.3v. digital ground should be provided by as continuous a ground plane as possible. while the analog and digital grounds are tied together inside the chip, it is recomm ended that they be tied together externally at a single point close to the chip as well. 0x5f event 9: any refer- ence changed from dis- qualified to qualified event 8: any refer- ence changed from quali- fied to dis- qualified address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x60 intr 7 enable intr 6 enable intr 5 enable intr 4 enable intr 3 enable intr 2 enable intr 1 enable intr 0 enable 0x61 intr 9 enable intr 8 enable address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
data sheet #: tm084 page 41 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet figure 17: power, ground and oscillator connections the external tcxo/ocx o master oscillator is connected to the mclk pin, and the mclk_frq_sel pin is tied low for 10mhz or high for 20mhz. .1uf ceramic 3.3v 1.8v 3.3v digital power inputs 1.8v digital power inputs .1uf ceramic .1uf 5 ohm,1/4w digital ground analog ground 1.8v analog power inputs STC4130 vdd33 (9) vdd18 (10) avdd18 (2) (x) number of pins mclk ocxo/ tcxo vss (16) avss (2) 10mhz/20mhz 1.8v mclk_frq_sel 0=10mhz 1=20mhz
data sheet #: tm084 page 42 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet mechanical drawing figure 18: mechanical dimensions * dimensions are in mm [inches] ordering information part number description STC4130 commercial temperature range model STC4130- i industrial temperature range model
data sheet #: tm084 page 43 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets data sheet
data sheet #: tm084 page 44 of 44 rev: p02 date: 12/5/06 ? copyright 200 6 the connor-winfield corp. all rights reserved specifications subject to change without notice STC4130 synchronous clock for sets functional specification data sheet information furnished by connor-winfield is believed to be accura te and reliable. however, no responsibility is assumed by conn or-win- field for its use, nor for any infringements of patents or other ri ghts of third parties that my result from its use. specifica tions subject to change without notice. for more information, contact: 2111 comprehensive dr aurora, il. 60505, usa 630-851-4722 630-851-5040 fax www.conwin.com revision date changes p00 5/12/06 in itial release p01 8/31/06 edited toc, pg.2 p02 12/5/06 added mechanical dimensions on pg.42, added industrial temp range part number

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